1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device. More particularly, the present invention relates to a semiconductor device having a vertical surround gate transistor (SGT) structure and a method of manufacturing the semiconductor device.
Priority is claimed on Japanese Patent Application No. 2007-200868, filed Aug. 1, 2007, the content of which is incorporated herein by reference.
2. Description of Related Art
In recent years, semiconductor technology has been applied over a wide range. High integration and low power consumption are strongly requested in integrated circuits from a general electronic equipment such as a dynamic random access memory (DRAM) and a central processing unit (CPU) to a special purpose for an automotive engine control and a universal satellite. In order to realize drastic high integration for semiconductor integrated circuits, there has been expected a new-structure transistor alternative to a conventional planar-type metal oxide semiconductor (MOS) transistor.
As an example of the new-structure transistor, there has been known a device using a silicon on insulator (SOI) wafer instead of a conventional silicon wafer. As shown in FIG. 11, a complementary MOS (SOI-CMOS) transistor 101 is formed on an SOI wafer 102. The wafer 102 includes a single crystal silicon wafer 102a, an embedded oxide film 102b, and a silicon layer 102c that are sequentially stacked therein. Here, the SOI-CMOS transistor 101 comprises a source region 103 and a drain region 104 formed in the silicon layer 102c, a body region 105 arranged between the source region 103 and the drain region 104, a gate insulating film 106 made from silicon oxide formed on the body region 105, and a gate electrode 107 made from poly-silicon formed on the gate insulating film 106. The source region 103 and the drain region 104 are impurity-diffused regions that are formed by ion-implanting n-type impurities in the silicon layer 102c. On the other hand, the body region 105 is an impurity-diffused region that is formed by ion-implanting p-type impurities in the silicon layer 102c. Side walls 108 made from silicon nitride are formed on both sides of the gate electrode 107. Furthermore, an interlayer insulation film 109 made from silicon oxide is stacked so as to cover the gate electrode 107 and the silicon layer 102c. Contact plugs 110a, 110b, and 110c are respectively connected to the gate electrode 107, the source region 103, and the drain region 104, and are formed in the interlayer insulation film 109.
According to the above SOI-CMOS transistor, the silicon layer 102c having an impurity-diffused region such as the body region 105 is insulated by the embedded oxide film 102b from the silicon wafer 102a. According to this, reduction of parasitic capacitance, prevention of latch-up, reduction of junction leakage, and suppression of short channel effect are accomplished. However, the SOI wafer is expensive compared to the conventional single crystal silicon wafer. For this reason, it is required for a transistor that uses the conventional single crystal silicon wafer to have the same characteristic as that of the SOI-CMOS transistor. The SOI wafer has a problem in that a self-heating effect occurs because thermal conductivities of the embedded oxide film and the silicon layer are largely different. Therefore, there is required a transistor in which heat generated by itself is effectively released similar to a conventional substrate. Furthermore, there is required a structure that can be applied to a floating-body-type transistor or the like that is used for a memory cell of capacitorless DRAM by making a design technique of a conventional transistor exploit. This structure can separate a substrate region and a body region so that many holes made by impact ionization can accumulate. However, manufacture of this structure has a problem in that it is difficult to dope by a conventional ion implantation.
Moreover, a planar-type MOS transistor having a conventional structure is improved according to the development of new materials for a high-k gate insulating film, a metal gate electrode, and so on. However, with a request of high integration for integrated circuits, a gate length has been reduced year by year. Within the next 20 years, it is thought that this integration necessarily reaches a limit. There is required development of mass production techniques to hold or improve ON currents with keeping Moore's law for a future. For this purpose, there is needed a structure that improves strict control for a distribution of dopant and control for a gate. For that purpose, it is necessary to form a source region, a drain region, and a body region that are obtained by controlling the distribution of dopant in a nanometer scale and strictly divide the regions.
On the other hand, if the body region has a channel formed therein, electric currents can not be controlled using only the small gate region. For this reason, a short channel effect occurs. It is necessary to guarantee a large gate region to form a channel in the whole silicon body region. Then, it is necessary to control electric currents and restrain a short channel effect. However, a planar-type transistor that is a conventional all-around gate transistor has complicated manufacturing processes.
On the other hand, as a vertical all-around gate transistor capable that is easily manufactured, there is developed a surround gate transistor (SGT) having a structure which is obtained by winding a gate insulating film and a gate electrode around a silicon pillar including source and drain regions and a channel region (refer to Japanese Unexamined Patent Application, First Publication No. H06-21467, No. H06-244419, No. H09-8290, No. 2005-64031, No. 2005-197704 and No. 2003-229494).
As shown in FIG. 12, a conventional SGT transistor 201 has a silicon layer 203 having a cylinder (pillar) shape, source and drain regions 204a and 204b positioned at upper and lower portions thereof, and a body region 205 positioned between the source and drain regions 204a and 204b. The SGT transistor 201 further has a gate insulating film 206 that covers the body region 205 around the silicon layer 203 and a gate electrode 207 via the gate insulating film 206. The source and drain regions 204a and 204b are impurity-diffused regions that are formed by ion-implanting n-type impurities in the silicon layer 203. On the other hand, the body region 205 is an impurity-diffused region that is formed by ion-implanting p-type impurities in the silicon layer 203.
However, a diameter of the silicon pillar must be increased to sufficiently guarantee the channel in the body region, in order to increase ON currents in the structure of such SGT transistor 201. For this reason, an increase efficiency of ON currents per unit area is low. Further, it becomes a problem that a threshold voltage changes because the diameter of silicon pillar becomes wide as a result.
Moreover, as the other transistor, a fin-type field effect transistor (Fin FET) has been known. In order to improve ON currents in the Fin FET, the silicon layer forming the channel must be thicker or be increased in a lateral direction. Therefore, Fin FET has a disadvantage in an area efficiency in the case of combination with or substitution of a conventional planar-type transistor. Moreover, when manufacturing a transistor with an ultrashort channel length, it is disadvantageous to form the ultrashort channel length because conventional ion-implantation processes are used. Since the shape of the transistor becomes higher in a direction perpendicular to the substrate or becomes longer in a direction of the substrate, the Fin FET has an unbalanced shape in which an original feature of the Fin FET cannot be utilized. For this reason, there is a problem in that it is difficult to manufacture itself.
Therefore, a double-gate transistor having a structure of a vertical transistor has been developed. The double-gate transistor has a structure by which leakage currents can be restrained when turning off the transistor by controlling the electric currents with two gates.
However, in the vertical double-gate transistor, its channel width must be lengthened to improve ON currents. For that purpose, gate electrodes must be arranged on both sides of the silicon layer forming the channel so as to sandwich the silicon layer. For this reason, there is a problem in that an occupied area per unit wafer area of the transistor becomes large.